Bare Die Test Handler
Inverter Wafer Reconstruct System
Be designed and developed for the reconstruction of frame wafers, supporting 100% visual inspection
It provides precise high-speed bare die reconstruction solutions. It supports inspection, transfer, and rearrangement from frame wafer to frame wafer. It offers state-of-the-art vision algorithms for the inspection of wafers and SPC.
Inverter Wafer Reconstruct System
Specifications
Device Category
Strip CSP/wafer-level CSP/bare chips/plastic devices
Loading Mode
Frame wafer
Unloading Mode
Frame wafer
Silicon Wafer Size
8 in/12 in
Device Size
1mm×1mm~17mm×17mm
UPH
Maximum: 15,000
2D Inspection Item
Dimension (diameter, size, width), spacing, position, angle
3D Bump Inspection
Coplanarity/probe marks/pad quality
Inspection Item
Dimensions/surface scratches/foreign objects/lack of corners/cutting quality/mark/direction/indentation quality/indentation offset
Optional Function
SECS/GEM
MTBA
≥3 hours
MTBF
≥168 hours
Dimensions
2.55m×1.62m×2.27m